Aportes a la reducción de consumo en FPGAs

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Politécnica Superior, Departamento de Ingeniería Informática. Fecha de lectura: 15-04-200

An fpga-based loco-ans implementation for lossless and near-lossless image compression using high-level synthesis

MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliationsIn this work, we present and evaluate a hardware architecture for the LOCO-ANS (Low Complexity Lossless Compression with Asymmetric Numeral Systems) lossless and near-lossless image compressor, which is based on JPEG-LS standard. The design is implemented in two FPGA generations, evaluating its performance for different codec configurations. The tests show that the design is capable of up to 40.5 MPixels/s and 124 MPixels/s per lane for Zynq 7020 and UltraScale+ FPGAs, respectively. Compared to the single thread LOCO-ANS software implementation running in a 1.2 GHz Raspberry Pi 3B, each hardware lane achieves 6.5 times higher throughput, even when implemented in an older and cost-optimized chip like the Zynq 7020. Results are also presented for a lossless only version, which achieves a lower footprint and approximately 50% higher performance than the version that supports both lossless and near-lossless. Interestingly, these great results were obtained applying High-Level Synthesis, describing the coder with C++ code, which tends to establish a trade-off between design time and quality of results. These results show that the algorithm is very suitable for hardware implementation. Moreover, the implemented system is faster and achieves higher compression than the best previously available near-lossless JPEG-LS hardware implementationThis research was funded in part by the Spanish Research Agency under the project AgileMon (AEI PID2019-104451RB-C21

Detección en tiempo real de fallos en piezas industriales con simetría de revolución

Se describe una aplicación para la detección de fallos en el ensamblado de muelles (resortes), utilizando la transformada polar discreta. La aplicación utiliza algoritmos de visión por ordenador. La velocidad de operación es crítica, dado que la respuesta debe ser dada en tiempo real. Los problemas a detectar son los defectos en uniones, la excentricidad de la pieza y estiramientos en el muelle. Se propone un algoritmo sencillo y eficiente, más la generalización de esta técnica para otros problemas similares.Área: Procesamiento de Imágenes - Tratamiento de Señales - Computación Gráfica - VisualizaciónRed de Universidades con Carreras en Informática (RedUNCI

High-speed FPGA 10's complement adders-subtractors

This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands.This work is supported by the Universities FASTA, Mar del Plata, Argentina, UNCPBA Tandil, Argentina, UAM ,Madrid, Spain, and URV, Tarragona, Spain; it has been partially granted by the CICYT of Spain under contract TEC2007- 68074-C02-02/MIC

Detección en tiempo real de fallos en piezas industriales con simetría de revolución

Se describe una aplicación para la detección de fallos en el ensamblado de muelles (resortes), utilizando la transformada polar discreta. La aplicación utiliza algoritmos de visión por ordenador. La velocidad de operación es crítica, dado que la respuesta debe ser dada en tiempo real. Los problemas a detectar son los defectos en uniones, la excentricidad de la pieza y estiramientos en el muelle. Se propone un algoritmo sencillo y eficiente, más la generalización de esta técnica para otros problemas similares.Área: Procesamiento de Imágenes - Tratamiento de Señales - Computación Gráfica - VisualizaciónRed de Universidades con Carreras en Informática (RedUNCI

Detección en tiempo real de fallos en piezas industriales con simetría de revolución

Se describe una aplicación para la detección de fallos en el ensamblado de muelles (resortes), utilizando la transformada polar discreta. La aplicación utiliza algoritmos de visión por ordenador. La velocidad de operación es crítica, dado que la respuesta debe ser dada en tiempo real. Los problemas a detectar son los defectos en uniones, la excentricidad de la pieza y estiramientos en el muelle. Se propone un algoritmo sencillo y eficiente, más la generalización de esta técnica para otros problemas similares.Área: Procesamiento de Imágenes - Tratamiento de Señales - Computación Gráfica - VisualizaciónRed de Universidades con Carreras en Informática (RedUNCI

LOCO-ANS: An Optimization of JPEG-LS Using an Efficient and Low-Complexity Coder Based on ANS

Near-lossless compression is a generalization of lossless compression, where the codec user is able to set the maximum absolute difference (the error tolerance) between the values of an original pixel and the decoded one. This enables higher compression ratios, while still allowing the control of the bounds of the quantization errors in the space domain. This feature makes them attractive for applications where a high degree of certainty is required. The JPEG-LS lossless and near-lossless image compression standard combines a good compression ratio with a low computational complexity, which makes it very suitable for scenarios with strong restrictions, common in embedded systems. However, our analysis shows great coding efficiency improvement potential, especially for lower entropy distributions, more common in near-lossless. In this work, we propose enhancements to the JPEG-LS standard, aimed at improving its coding efficiency at a low computational overhead, particularly for hardware implementations. The main contribution is a low complexity and efficient coder, based on Tabled Asymmetric Numeral Systems (tANS), well suited for a wide range of entropy sources and with simple hardware implementation. This coder enables further optimizations, resulting in great compression ratio improvements. When targeting photographic images, the proposed system is capable of achieving, in mean, 1.6%, 6%, and 37.6% better compression for error tolerances of 0, 1, and 10, respectively. Additional improvements are achieved increasing the context size and image tiling, obtaining 2.3% lower bpp for lossless compression. Our results also show that our proposal compares favorably against state-of-the-art codecs like JPEG-XL and WebP, particularly in near-lossless, where it achieves higher compression ratios with a faster coding speedThis work was supported in part by the Spanish Research Agency through the Project AgileMon under Grant AEI PID2019-104451RB-C2

Low-power FSMs in FPGA: Encoding alternatives

The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57% can be achieved selecting the appropriate encoding. An areapower correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.Ministry of Science of Spain, under Contract TIC2001-2688-C03-03, has supported this work. Additional funds have been obtained from Projects 658001 and 658004 of the Fundación General de la Universidad Autónoma de Madrid